veriloggen
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Creating input with literal BW in the form of [n:0] instead of [n-1:0]
I am using a python list comprehension to create on the fly the inputs ports for my module.
inputs = [m.Input (str(name), bw) for name,bw in ports_dict]
Where ports_dict
is a dict of this shape: {'one_port_name_of_bw_3' : 3, 'other_port_of_bw_1' : 1, ... }
I would expect the m.Input
class to have these written out as
input [2:0] one_port_name_of_bw_3,
input other_port_of_bw_1
Instead I am having
input [2-1:0] one_port_name_of_bw_3,
input [1-1:0] other_port_of_bw_1
Input
class inherits from _Variable
, which is defined as
class _Variable(_Numeric):
def __init__(self, width=1, dims=None, signed=False, value=None, initval=None, name=None,
raw_width=None, raw_dims=None, module=None):
Tried some of these extra args but I do not think any of them allow for this funcionality? raw_width
looks like what I want but I could not get it to work. The idea would be maybe to pass a tuple (2:0) and so have a [2:0]
bitwidth? Hmm, wait, but what would happen with the 1 value then? Anyway you get my point, maybe this is already implemented somehow and I am missing it
Thanks!