Nic30

It seems to me that it is only required to replace some parts of logic which generates a positions of nodes in columns. I did some proof of concepts but...

https://github.com/Nic30/hwtIde/blob/master/hwtIde/static/hls/connections/a_star.js Long story short: I tried it and it worked somehow, but it was definitely bad idea (as there is endless number of corner cases..) so I deprecated the idea...

I have tried genetic alg. (pagmo2) and it worked somehow, but it was bellow the expectations in terms of performance and quality. > i.e Machine Learning It seems to me...

I did not want to say that nothing better exists. Feel free to search for a while, my knowledge of this agenda is 1y old... If you find something please...

Using Ubuntu 21.10 with LLVM-13 (`llvm-dev llvm liblldb-dev llbd` packages) compiled with gcc 11.2.0 it seem to be working fine.

XDC is a subset of TCL, there is a ANTRL4 grammar for TCL. There is a grammar for ANTRL4 https://github.com/Nic30/hdlConvertor/blob/master/grammars/tcl.g4 GitHubNic30/hdlConvertorverilog and vhdl parser module for python. Contribute to Nic30/hdlConvertor...

There is also [coreir](https://github.com/rdaly525/coreir). The open hardware community really needs such a language, It is quite clear. I think that FIRRTL is good enough and already has large community. It...

@kc8apf why are you not using ANTRL4 C++ runtime?

@dvc94ch Is it possible to have more than single clock domain in current FIRRTL?

@seldridge After I finish UVM like API for Verilator (+- 1 month) I can help with C++/Python FIRRTL. I have experience with ANTRL4, hardware design, etc. It would be great...