Nic30

Hello, actually today I was doing something similar (I parsed and elaborated Verilog design with DSPs and I used d3-hwschematic to see how things are dependent on parameters. I used...

> which source to use? https://github.com/forflo/yodl https://github.com/ghdl/ghdl-yosys-plugin But I am not sure how stable it is. The reason why I am thinking more about yosys than pure GHDL is that...

Use this flag to debug what is actually taking so long: https://github.com/Nic30/d3-hwschematic/blob/master/src/d3-hwschematic.js#L65 I think that the problem was the the layout (the algorithm which resolves how wires will be routed...

Example of treelist in d3.js http://bl.ocks.org/thehogfather/0e48ec486abbd5be17d7 @xkotek07 maybe we need something similar.

We may also want to add help lines to visualize hierarchy more explicitly as hierarchy can be quite deep. 

After this issue is solved the json will contain also ports which are collapsed by default https://github.com/Nic30/hwtGraph/issues/1


Currently all this is possible from d3js but we need the tutorial for this or custom methods on the scheme object.

Hello, quick answer: You need to convert VHDL/Verilog to the suitable JSON. Long answer: In order to do that you need to parse VHDL/Verilog and perform the complete analysis off...

The gui can display anything. The parsers which can parse the full informations about the connections from the hdl does exists. However there is not a final piece of the...