DBT-RISE-RISCV
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Minres
An instruction set simulator based on DBT-RISE implementing the RISC-V ISA
When the trap handler (MTVEC) resides at an address that returns a TLM error, the debugger will lose control of the session. Specifically we end up in a loop where...
When attaching the debugger it seems that two single-steps are required to actually single step the first instruction. Turning on verbose debug, the first single-step results in a memory read...
We need a way for a debugger to regain control while the core is in in WFI. The [RISC-V Debug Specification](https://github.com/riscv/riscv-debug-spec/releases) states in section 4.3: > If halt is requested...
Is there a document/file in the repo that describes the build dependencies with respect to other repos (for example, which DBT-RISE-Core commit is compatible with a given DBT-RISE-RISCV commit)? We...
With the current implementation of the TLB, only page table walks get cached, the checking whether the PTE is valid is done every time. This can be mitigated by: -...
Currently JIT backends do not work as intended with the MMU. The reason for that is the fact that fetches for entire basic blocks are done at the start of...