Jim Lewis

Quick Update. OSVVM was using external names for data structure access. With the 2021.06 and 2021.07 releases, we created singleton data structures for Memory, Scoreboards, and Coverage. As a result,...

@avelure You are asking about a shared variable of an ordinary type. You do understand that these were deprecated and removed by VHDL-2002 right? What do you expect a simulator...

@avelure Just so we are clear, deprecated and removed. If you are looking for language compliance, a compliant tool would fail with an error if you use a shared variable...

The current version of OSVVM 2021.09 passes regression with the current version of GHDL with the exception of Axi4Lite. Axi4Lite needs an update similar to what was done for Axi4...

@eabtioglu The AXI spec says that you can use AXI4 Full Manager in place of Axi4Lite as AXI4 Full simply has more signals (that a subordinate can ignore) and do...

There are 2019 code examples at https://gitlab.com/synthworks/VHDL_2019. These are the ones I wrote for the presentations I did with Aldec. [LCS-2016-002](http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/LCS2016_002) will help with some additional data structures I have...

VHDL-2019 gives a mechanism to put a date code that you can use as a revision indication. Long term - and perhaps longer for synthesis tools - the language will...

Seems like there are two questions: 1) First, the OP are conditional assignments allowed in processes in VHDL-2008. Yes. Absolutely. I would not change the code unless I was the...

Continuing with 2: A process without a sensitivity list immediately starts running and does not suspend until it hits the first wait statement.

@ozbenh A property of combinational logic is that it is sensitive to all signals that are read in the process. Hence, in RTL for combinational logic, "all" is the right...