Dolu1990

Supporting SpinalHDL

21

As a way to scale up SpinalHDL we are looking at : - Companies sponsorship as a way to provide funding to the SpinalHDL maintenance - Open a https://opencollective.com/ or...

Cross platform toplevel pin mapping definition

7

For exemple, Xilinx and Altera have their own file format to specify mapping between design pins and package pins (+ specify pin technologies, current, terminaison, ...) It could be great...

Contribution checklist

3

Contributor Checklist - [x] Did you add some test code? - [x] Did you add appropriate documentation in docs/src? - [x] Did you state the API impact? - [ ]...

## Compiler version 3.1.3 / 3.2.0-RC1 ## Minimized code https://scastie.scala-lang.org/73ZtErR0QNGKc7VSiP4XEg ```Scala import scala.language.implicitConversions class Data //Model a data instance class HardType[T T) //Model a Data factory object HardType{ implicit def...

Feature : verilog's signals parameter ex : (* KEEP = "TRUE" *)

1

Hi, It would be useful to alow to set custom parameter (verilog backend) to signals and ram. For example with xilinx FPGA : (\* KEEP = "TRUE" *) reg [10:0]...

No definition of 'channel' in I/O Ordering

4

Hi, In the `RVWMO Explanatory Material`, in the `I/O Ordering` section, there is the notion of `channel` used multiple times. The issue is that there is no definition of what...

Using spike in a lock-step hardware simulation

16

Hi, I recently developped a RISC-V OoO core and used Spike as a reference model in the verilator simulation of the hardware core. Got the simulation to keep spike and...

Hi, On a RV32IMAFD config (VexRIscv), running linux, i got the following trap from opensbi (0.8, compiled by buildroot) : ``` sbi_trap_error: hart0: trap handler failed (error -2) sbi_trap_error: hart0:...