Rei_Fu_Zhang

您好，我在進行 make verilog 這一步時，發現內存不夠，因此按照上述步驟將內存需求降為10G，不過我在non-inclusive L3這一步發現機器沒有反應(沒有報錯也沒有反應)，我大約兩次都等了兩個小時，也發現內存始終都保持著高占用的情況，請問是我等地不夠久還是需要另作調整(? 謝謝

感謝回復!那請問香山生成的東西，我只需要將 XSTop.v 加入vivado 專案之中，其他外設自行定義，還是需要添加其他生成的資源呢(我嘗試把整個 build 拉進專案之中，結果vivado跑不太動)? [TRANSLATION] Thanks for the reply! I only need to add XSTop.v to the vivado project, and define other peripherals by myself, or do I...

了解了，感謝你的細心回復!有遇到問題還要再麻煩了! [TRANSLATION] I see. Thank you for your careful reply! Have encountered the problem even again trouble!

> 请手动把 DebugOptions 中的 AlwaysBasicDiff 参数设置为 false 不好意思，請問是 vivado 之中的選項嗎(? 我在2022.2的版本中沒有找到

你好，修改完後依舊有錯誤的檔案，大多為sim相關的 [TRANSLATION] Hello, there are still wrong files after modification, most of them are SIM-related

Thank you very much for your reply sir, I would like to ask you the second question, may I ask if the scope of my modification will go beyond the...

Thank you sir!

> No, you should not need to modify anything beyond the board/C1100 folder. > > You can consider adding C1100 into [board/rocket-freq](https://github.com/eugene-tarassov/vivado-risc-v/blob/master/board/rocket-freq) to get higher CPU clock frequency. The default...