Baungarten-CINVESTAV

Testbench gives multiples 1'bx when use high number of inputs/outputs

4

Hello every one, As the title says i had a couple of erros when i used mutiples i/o. Trying to find the mistake, i simplified my modules on a couple...

Placement Resizer optimization error with recently version of OpenLane

11

### Description Hi all, I create this issues due to i'm working on a project with OpenRAM, i create a module that combine two SRAM macros to work as one,...

Head Maps Power Density 0.00 fW

10

### Description The OpenROAD -GUI Head Map Power DEnsity view shows 0.00 fW when loading .def and .lef files or when the .odb file is loaded ### Expected Behavior 1)...

Error in the path, gate level simulation

1

The path of `caravel_core.v` is wrong on [includes.gl.caravel_user_project]( https://github.com/efabless/caravel_user_project/blob/main/verilog/includes/includes.gl.caravel_user_project ) it must be change from: ``` # Caravel user project includes -v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v -v $(USER_PROJECT_VERILOG)/gl/user_proj_example.v -v $(USER_PROJECT_VERILOG)/gl/caravel_core.v # default should...