BarebitOpenSource

Thank you for spotting it, it's a typo. It takes some time to fix it. Relevant link: http://ref.x86asm.net/coder64.html#modrm_byte_32_64

Good question. If I remember well, SETcc with r/o field different from `0` caused invalid opcode exception on (at least few) Intel processors when I checked it many years ago....

Thanks for pointing this out. The `FCOM` without operands must be exactly the opcode `D8D1` (yes, the opcode extension `2` is redundant here). In other words, whenever you disassemble `FCOM...

If I remember well, you're right, but I need to check it once more.

As for the AVX, I need to add it too, and you seem to understand the XML structure and the rules quite well. Could we collaborate on AVX? I think...

I looked into it finally. The answer to the first question is that you're right, two entries are not needed. The answer to the second question: we need to indicate...

Good point. I don't have the original Intel manual that's been around when I wrote the reference but I'd swear the operation was described as follows: 1. the immediate value...

This is what I've been always fighting with. Intel never bothered to create formal strict syntax rules for the instruction set and the syntax changes in time. Long time ago,...

I don't have time to add them. We also need to design first how AVX instructions should be added because they use backward incompatible instruction format.

Do you have experience with coding with AVX instructions? The most important is figuring out AVX [instruction operand codes](http://ref.x86asm.net/#Instruction-Operand-Codes). These can be seen in the geek editions, see for example...