Barebit
Opcode field for SETcc unnecessary
The reg/opcode field (o in the table) of the ModR/M byte for all of 0x0F90-0x0F9F (SETcc) has 0 in the sheet, which I believe is misleading.
I don't see this in the manual (Intel® 64 and IA-32 Architectures Software Developer’s Manual March 2017 version); usually represented as /0 (for eg. C0 /0 ib for ROL r/m8, imm8).
Good question. If I remember well, SETcc with r/o field different from 0 caused invalid opcode exception on (at least few) Intel processors when I checked it many years ago. Do you happen to Intel processor to check r/o different from 0?
As for the Intel manuals, they don't cover many corner cases unfortunately. Out of curiosity, AMD manual explicitly stated that the r/o field is unused.
