Jalali
Jalali
Hi @arshadrohan5, there's an other PR for the Zcmp instruction for the Specification
Hello @MikeOpenHWGroup , This one of our next steps of enhance the UVM CVA6 env, we want to make this env re-usable using the RTL configuration (CVA6Cfg), in this way...
@MikeOpenHWGroup could you check the uvme_cva6_cfg.sv, now it has values from the RTL configuration !
> @AyoubJalali Any idea ? we can't raise this exception, because we support C extension, so it means that we should Execute on an address half-work misaligned LSB bit !=...
> Do you mean when writing `b'xxxxxx10` where x can be 0 or 1 in a `pmpxcfg` byte, the result is `pmpxcfg` equal to 0? yes
Yes you right, I double check the fix !! Thanks @Moschn
The problem is that if I wanna execute a test with 3 source registers, i should change in the **araine_pkg**, it's like i change in the RTL, and i don't...
what I observed is the CVA6 can read/ write and execute from address 0x0 to 0xffff_ffff (virtual address), we need to resolve this, this is not right
> Now RVFI provides extensive information when exceptions are triggered. @AyoubJalali : is the information provided by RVFI sufficient? If so, can you close this issue? good for me
Hello @MikeOpenHWGroup indeed **_+ntb_random_seed_** it override but not by **core-v-verif/cva6/sim/cva6-simulator.yaml**, it's the --sv_seed option in **_verif/sim/cva6.py_**