Jalali
Jalali
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Hello, @JeanRochCoulon @ASintzoff While improving the CC of the...
Hello, So I notice that there's some covergroup for c.jr & c.jalr has : cp for rd (i don't think these instructions use rd) https://github.com/openhwgroup/core-v-verif/blob/05ba4eb0cf6296bf35f487fbe2ab01e532d0fe26/lib/uvm_agents/uvma_isacov/cov/uvma_isacov_cov_model.sv#L985 also for rs1 cp, we...
The cva6.py script use the YAML description to generate random tests, the problem here in the compressed instructions, actually these instructions are active by default, so to disable these instructions...
Hello, @MikeOpenHWGroup @silabs-robin Always in isacov, I notice that there some cover group like, cp_rs1_toggle & cp_rs1_value in c.mv & c.add instructions, but these instructions don't use rs1, so it's...
Hello, @silabs-robin I notice in https://github.com/openhwgroup/core-v-verif/blob/master/lib/uvm_agents/uvma_isacov/cov/uvma_isacov_cov_model.sv there is some incorrect coverpoint declaration for some **C_TYPE** like **(CIW, CL, CS, CB)**, https://github.com/openhwgroup/core-v-verif/blob/05ba4eb0cf6296bf35f487fbe2ab01e532d0fe26/lib/uvm_agents/uvma_isacov/cov/uvma_isacov_cov_model.sv#L1293, so in this example we create a coverpoint for...
Hello @JeanRochCoulon @ASintzoff , So I have notice some incorrect argument value in get_instr_value_type(bit[XLEN-1:0] value, int unsigned width, bit is_signed) for some C extension instruction,starting from https://github.com/openhwgroup/core-v-verif/blob/9962aebe36b339bf88ca7e1d8cb3143e10edbda4/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv#L232 to https://github.com/openhwgroup/core-v-verif/blob/9962aebe36b339bf88ca7e1d8cb3143e10edbda4/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv#L279 ,...
Hi @MikeOpenHWGroup ,I have been working on reusing the ISACOV agent for CVA6, and i notice in the cover group declaration related to C extension, specifically rv32c_jal_cg & rv32c_j_cg you...
Hello, @ASintzoff @JeanRochCoulon I have been using the RISCV-DV (I use VCS to compile and run the generator), to improve the Code coverage of the CVA6 Core processor, by generating...
This MR content 2 commits : 1. Connect CSRs info coming from RVFI (implamanted recently by @ycasamat) in the testbench 2. Update target simulation (use CV32A65X)