Rachit Nigam

Also, FWIW, `match_element` is a classic example of a "combination components" that are not supported by Calyx right now (as pointed out by @sampsyo).

Yeah, I just implemented a fix for the problem in #624 and realized that this way of "passing registers/memories by reference" doesn't actually work at all.

> That strategy ends up creating a cycle on the subcomponent's done signal for reasons I can sorta-kinda see but can't really articulate having to do with the super-component's go...

Yeah, that seems to be the case---sequential implementation of "pass-by-reference" works fine. Maybe we should require that the group using `mem_done` still uses a component-defined cell for its `done` signal...

Another ponderous solution to this problem, or rather a guarantee that should possibly be provided by the compiler, is that there is no combinational path between a component's `go` and...

@EclecticGriffin has there been progress on this and is this important for the paper?

Removing the bug label because the PR above fixes the immediate problem.

For reference: We originally implemented the `initial` block stuff because we kept encountering a zero-time reset bug in Verilator. We can try removing the initial blocks entirely and see if...

See the original bug (https://github.com/cucapra/calyx/issues/284) and the fix (https://github.com/cucapra/calyx/pull/288)

I think it'd be better to make icarus-verilog tests run in the integration test suite? In general, icarus is faster than Verilator so at some point, it'd make sense to...