Rachit Nigam

Awesome!! > Also, is there some way for fud to include external verilog? So the `extern` keyword specifies the path to the verilog file and the Calyx compiler will attempt...

@andrewb1999 if its okay with you, I'm going to close this issue for now. We've added a new primitive for sequential reads (#1145) and your compiler can generate new memories...

You probably need to reset the component state before running it again after clock gating

One question that came up during while discussing this with @calebmkim was whether disabling the clock to a part of the circuit leaves all the registers in an indeterminate state...

We can revisit this in the future if we ever implement an ASIC backend

Argh, just came across a slightly different version of the above example where the control program is: ``` seq { false; par { seq { true; zero_f0; } zero_f0; //...

Nope, incorrectly closed. The problems is explained here: https://github.com/cucapra/calyx/discussions/651#discussioncomment-1324881

The integration test for `durbin` is disabled because of this issue: https://github.com/cucapra/calyx-evaluation/commit/115b282c8452a070bf29537b6e0867d8a77573ed

This would be great and is something we should prioritize doing before the end of the summer!

Just to clarify, this is not about data format but data structures right? I remember this came out of a conversation about supporting source-level data structure debugging.