Rachit Nigam

Looks like the `resource-sharing` pass causes this problem. Running the benchmark with `-d resource-sharing` generates valid verilog and generates the right values.

Minimal test case: ``` import "primitives/core.futil"; component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) { cells { add10 = std_add(32); add7 = std_add(32); add8...

https://github.com/verilator/verilator/issues/3146 could be the potential problem

Argh, resource sharing might be a fundamentally broken pass. It might only make sense to share sequential components.

@sampsyo @EclecticGriffin and I discussed this problem and we agree that the generated code is "valid" in that the combinational loop is stable. However, we need to do some digging...

This plan certainly sounds like it'll be a worthwhile investment in the long run. The question for us is what do we want to accomplish in the next month. We...

Looks like pretrained models can be found here: https://github.com/onnx/models

Experiment to see if fan-out problems can be fixed using this: - Write generator for generating high fanout programs (with some variable to control fannout) - run synthesis until this...

The problem that @paili0628 ran into happens because `clk` and `reset` signals are special: they are automatically threaded through the design into the primitives that define them using the `clk-insertion`...

So the weird thing is that the parser automatically adds all of these signals to a component's definition if and only if it is missing them. For example, a component...