Rachit Nigam

Yeah, this looks like a cool way to use the cells. This is besides the point you were making but it's rarely worth sharing combinational components like `neq` precisely because...

I think it would be useful to open an issue to change the systolic and NTT frontends to use this new interface just so that we can have more users...

I think we should eventually move AXI out of thr compiler and mame it a standalone tool

Thanks for opening this! As I mentioned, the right solution is implementing https://github.com/llvm/circt/issues/4831 but in case this becomes a blocker, let me know @zzy666666zzy and I can try to fix...

If I redesigned Calyx, I would make registers and wires abstract in the IR like @cgyurgyik did in the MLIR dialect. There are a lot of passes, analyses, and optimizations...

The more things you have in the IR, the more things you have to worry about optimizing so we generally prefer having canonical versions.

I'm going to centralize the conversation about this topic to this issue. First off, some context: - https://github.com/cucapra/calyx/discussions/588 : Attempted to highlight the problems with the absence of validity of...

Maybe the "Low Priority" tag is in order? The task does seem pretty actionable but probably not critical for anyone's use. However, I think in the past @sampsyo has voted...

For some of these issues, like `with` not being supported, we should resolve the long-running `with` discussion and decide if we want to get rid of it completely or not.

I think at the Calyx level, this would be easy to do. The big question is how do we correctly parameterize primitives like memories to actually accept zero-bit ports. For...