Rachit Nigam

I think the lower-unroll pass depends on the hoistMemory stuff running before it and the hoistSlowOp stuff running after it so we can't just combine them into one pass.

This is not sufficient to reproduce the bug. On a broader note, it seems hard in general to build upon a broken backend--we have to assume that the backend is...

I thought the “avoiding bad parts” to be statically definable bad parts. HLS tools add new bugs every version. Trying to prevent those bug seems like a losing battle—we’d have...

Spatial [inlines functions](https://spatial-lang.org/conv). See under "Using Functions".

## Affine functions Real reusable functions which specify how many instances of RTL blocks implement them. For example (made up syntax): ``` def foo{N}(...) ``` creates `N` instances of the...

### `--explain` flag for errors When a type error occurs, use the (currently non-existent) machinery to draw out an abstract design and show why the circuit diagram is invalid. CC...

### C2Fuse Write a compiler that converts a random C/C++ program into a Fuse program. Having feature parity with Vivado HLS (i.e. C2Fuse fails iff HLS fails) would be really...

## Fully serializable IR/AST Tools like Jason’s automatic loop optimiser might want to use fuse instead of vivado HLS to write transformations and verify that they don’t violate the safety...

## Demonstrate common SW compiler optimizations don’t make sense for HW Most HLS tool from the past decade rely on LLVM/GCC toolchain to get SW optimizations “for free”. However some...

## HLS for Digital Signal Processing According to [this overview doc](http://www.ti.com/lit/wp/spry281/spry281.pdf?DCMP=leadership&HQS=ep-pro-dsp-leadership-150427-problog-wp-en) by texas instruments, DSPs have similar restrictions to FPGA programs (statically known loop bounds/estimates for instruction pipelining etc.) Might...