Mike Thompson

icon indicating a website link http://www.openhwgroup.org icon indicating an email [email protected]

icon company @openhwgroup icon location Ottawa, Ontario, Canada icon location Functional verification of RTL for ASICs and FPGAs. Sole Proprietor at Covrado and Director of Engineering, Verification Task Group at the OpenHW Group.

Results 496 comments of Mike Thompson

CORE-V SDK package for Ubuntu 22.04

Hi @promodkumar-ashling, this Issue has not been updated for a couple of months. What is the current status?

Which exceptions and interrupts can be deligated?

Hi @ASintzoff and @JeanRochCoulon, I just noticed that this Issue has both `CV32A60AX` and `notCV32A65X` labels. Is that correct?

Update the interrupt vector table in the documentation

Hi @DanieleParravicini-Synthara. I recommend that we have a (virtual) in-person discussion with @davideschiavone and @MarioOpenHWGroup before we proceed much future with this PR. In the meantime, you will need to...

Update the interrupt vector table in the documentation

> In the meanwhile I will ask to complete the ECA Hi @DanieleParravicini. I see that you are now properly covered by the ECA using your Synthara credentials. However, there...

RVFI depends on the testbench

Indeed. AFAIK, there is no phase difference between the `clk_i` input to this module and `clknrst_if.clk` in the UVM "clk-and-reset" interface. So, maybe it is just as simple as replacing:...

RVFI depends on the testbench

Reassigning this Issue to myself and @cairo-caplan to discuss. I agree that what we have in place now will work and will also keep Verilator lint happy. Having said that,...