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lowRISC
[chip-test] chip_sw_usb_suspend
Test point name
Host side component
SystemVerilog
OpenTitanTool infrastructure implemented
Unknown
Contact person
@a-will
Checklist
Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
@alees24 (a new starter at lowRISC) is taking a look at USB device TLT, I've put him in planned assignee for now as he's ramping up currently rather than actively working on any particular test.
Deferring to V3 / M7 as P2 as discussed in today's triage meeting and with @alees24.
We've discussed in the triage meeting that we should prioritize this chip level test as it covers an relevant use case @alees24 . Would you mind taking a look at this please?
This is a very old test point description; a more comprehensive set of 7 tests exists in daft PR #23200 which have been run on all targets including ES SiVal. The main problem with SiVal/ES/FPGA tests is each party having appropriate time out values for the other party (USB host software and device). The chip sim is an easier, more predictable target not subject to the vagaries of non-real time operating systems and variable workloads. I've added an estimate of 2 days to finish off the tests for ASIC-level chip sim only; they have previously run there a number of times, but may have suffered bit-rot.
Thanks for this updated information, @alees24. If you could indeed prioritize finishing the DV TLTs that cover this testpoint, that would be great! Please feel free to update the test point definition while you work on this.