ztachip

Instructions to save/restore register to stack is taking 2 clock each

12

I wrote a simple task switching that save registers and restore registers // Save registers sw s0,4(sp) sw s1,8(sp) sw s2,12(sp) sw s3,16(sp) : : // Restore registers lw s0,4(sp)...

Axi4Crossbar

1

Can Axi4Crossbar connect AXI ports from different clock domains?

Setting for user_clk

1

I assume that user_clk is the clock for the AXI interface. Do I have a choice on this clock? Can I set user_clk to any clock value? Thanks

Your project is very interesting. I think this is very useful for DomainSpecificArchitecture. Which many say is the future of computing. I also created an opensource github.com/ztachip/ztachip along the line...

Vexiiriscv instructions

4

Could you provide some instructions on how to install and use this new version. Is it similar to VexRiscv? Thx

Help for custom instruction

5

I try to create a custom instruction for fast context switching The opcode will save a register value and at the same time restore the register to last saved value....

I would like to port TinyChatEngine to a proprietary hardware accelerator platform based on FPGA. I would like to run VILA model. Your implementation seems to be optimized for CUDA...

In your model list, VILA-3B was missing. Do you plan to support that Also using TinyChatEngine, can it analyze video with VILA

llm.c for inference

2

Do you have the equivalent simple C implementation of LLM but for inference of LLAMA models. I am trying to build a FPGA accelerator for LLM and a simple reference...

Is it possible to replace all calculation in float32 with float16? How would this impact accuracy? Is this attempted before?