ztachip

I am using AXI for bus. package vexriscv.VexRiscvForSim import spinal.core._ import spinal.lib._ import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} import spinal.lib.bus.amba3.apb._ import spinal.lib.bus.amba4.axi._ import spinal.lib.bus.misc.SizeMapping import spinal.lib.io.{InOutWrapper, TriStateArray} import spinal.lib.misc.{InterruptCtrl, Prescaler, Timer} import spinal.lib.soc.pinsec.{PinsecTimerCtrl,...

Outside of VexRiscv, I instantiated some logic to split iBus/dBus between an internal RAM block (16K) and external memory (256M) based on memory address region. During the test of doing...

To make sure all data access fit the DataCache, My stack is only 2K. And my DataCache is 8K/2way

There are no external memory cycles. The program simply pushing and poping register values to/from stack that fit entirely in cache. But can we expect code below to take just...

Sure, are there any VexRiscv internal signals you like me to show on wave file? ________________________________ From: Dolu1990 ***@***.***> Sent: February 7, 2024 11:00 AM To: SpinalHDL/VexRiscv ***@***.***> Cc: ztachip...

I assume you want wavefile from Verilator? My code has VHDL so Verilator does not work for it unfortunately, but I can try to create a test program with Verilog+Verilator...