Zephyr

openKylin TianJin Currently working on box64 for RISC-V

Results 2 issues of


                                            Zephyr

[RV64_DYNAREC] Modify some functions related to caching and SSE to support AVX

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About emulating AVX instructions on RISC-V

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Now that RISC-V dynarec supports vector instructions, will AVX be emulated with scalar instructions?