ptitSeb
About emulating AVX instructions on RISC-V
Now that RISC-V dynarec supports vector instructions, will AVX be emulated with scalar instructions?
We need to refine current RVV support, add MMX support for RVV, and add xtheadvector support... so AVX will come after.
We need to refine current RVV support, add MMX support for RVV, and add xtheadvector support... so AVX will come after.
Will that be followed up by emulating AVX with RISC-V scalar instructions? Isn't it enough to use RVV
There is always the interpreter when opcodes are not implemented in the dynarec.
Idealy, the dynarec would run on all CPU, so scalar as a minimum, rvv/xthreadvector if available. But it's a mater of time/work. It's still a lot of work to implement all those opcodes.
What are you interested in with AVX emulation @zohanzephyr ?
There is always the interpreter when opcodes are not implemented in the dynarec.
Idealy, the dynarec would run on all CPU, so scalar as a minimum, rvv/xthreadvector if available. But it's a mater of time/work. It's still a lot of work to implement all those opcodes.
What are you interested in with AVX emulation @zohanzephyr ?
I noticed that an application I was running utilized AVX instructions, so I'm interested in learning more about this and any related future plans.
AVX for RISC-V is mostly implemented now.
https://github.com/ptitSeb/box64/releases/tag/v0.3.8
