Zbigniew Chamski

The `ICACHE` and `DCACHE` CSRs are now supported in Spike through Spike extension `cv32a60x`. While the extension may get renamed (currently it only provides the two CSRs mentioned), I propose...

Hi @dvusingh, please make sure that you activate Verilator-based RTL simulations and that you enable the waveform generation by setting one of the environment variables that control waveform generation: *...

Further discussion of waveform generation (VCS use, limitations etc.) is given in the toplevel `README.md` of the `cva6` tree (section "Waveform generation").

Hi @dvusingh, did you get a chance to test the instructions above? If so, did they work for you?

@JeanRochCoulon, did you mean 5.008? Odd minor versions of Verilator are development/unstable ones.

This is a topic still open as the main focus remains on verification, leaving core-environment interactions at lower priority.

> Hello @Moschn @zchamski is trying to remove the VERILATOR ifndef directives from RTL. From Zbigniew, I understood that Verilator 5 supports the assert. In that case, all the directives...

I'm getting the issue on the front burner again. As of commit 2745f3edc there are 44 occurrences of `ifndef VERILATOR` in total: 23 in the `core` and 21 in `corev_apu`...

Based on the User Manual info, the exception should be triggered on the RTL side in the first place. On the Spike side the default setting is 2GB so the...

OK, so that's an RTL issue (access outside the mapped space should be detected). @JeanRochCoulon, what's your view on this?