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openhwgroup
[Spike] : Mismatch of address mapping between spike & RTL
Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
Bug Description
Hello, So after the merge of spike tandem, one of the directed tests that I wrote (to cover some corner cases in the ISACOV) failed, in this case spike reach his maximum steps, so after a quick debug, I found that spike raise an exception of loadaccess_fault on an address (example : 0xffff_fff0), in the opposite side the CVA6 does raise any exception and threat the address in his valid range.
So to reproduce the problem you only need to execute the command line :
### python3 cva6.py --testlist=../tests/testlist_isacov.yaml --test load_reg_hazard --iss_yaml cva6.yaml --target cv32a6_embedded --iss=vcs-uvm,spike (run it in cva6/verif/sim) of course using the new spike (cva6 HASH 5e68fc0a3fde3333d645d0b43fbce58bebabe6cf)
Following the specifications, this address is out of both ExecuteRegion and CachedRegion .
https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/Parameters_Configuration.html#parameters
Based on the User Manual info, the exception should be triggered on the RTL side in the first place. On the Spike side the default setting is 2GB so the access should succeed unless tandem parameterization clips the range already to 1GB (32'h4000_0000).
OK, so that's an RTL issue (access outside the mapped space should be detected). @JeanRochCoulon, what's your view on this?
@zchamski To my mind, test is maybe wrongly compiled/linked. Why 0xfffffff0 address is acccessed ? Of course cva6 does not implement this address but the test should not use this address.
Looking at the code, the access is explicitly coded as lw zero, -16(zero), so the compilation flow only generates the corresponding instruction.
OK, so that's an RTL issue (access outside the mapped space should be detected). @JeanRochCoulon, what's your view on this?
Any news from the CVA6 spec and/or implementation side?