Ronen Ulanovsky

Hi @taks @Rahix, thanks for the work on the crate! Just wanted to chime in wrt release timing of this PR. We're currently using this branch with `esp-idf-hal` (`esp-hal` also...

@MabezDev, I noticed the same bug when formatting f32 on release mode. Tested on 1.65.0.0. It's both misprinting and crashing with f32 and f64. f32: ``` I (312) esp_spinlock_repro: counter...

@MabezDev @N3xed @ivmarkov I significantly reduced the minimal reproduction and moved it to `no_std`. I also updated the `README.md` and added the disassembly diff (sort of). ```rust #![no_std] #![no_main] use...

@MabezDev this is getting to the limit of what I can do, but compiling the following branch: https://github.com/zRedShift/esp-spinlock-repro/blob/without-heapless/src/main.rs (without `heapless`) with thin and fat LTO and comparing the disassembly (the...

Narrowed it down to `4200052f 00 4e a1 sll a4,a14` in the fat lto file it should be `4200052f 00 4f a1 sll a4,a15`, right before the CAS loop.

@japaric FYI, `core::net` or [ip_in_core](https://github.com/rust-lang/rust/pull/119276) lands as stable in Rust 1.77, so depending on the MSRV policy, it obsoletes any need for no_std implementations to hold their own structures for...

@ramtej AFAIK, LLVM plain old doesn't support/recognize the hundreds of DSP instructions, so to use inline assembly it would require either adding them all, or using the escaped binary opcode...

@ramtej awesome find. This will also help with ESP32P4's custom RISC V DSP extensions, when it comes out. I haven't investigated it yet (I was actually planning on just writing...

I've been warming up with some Xtensa LLVM backend contributions over the last few days. My end goal is fast (scalar or vector) DSP, for ESP32S3 in Rust, since I'm...

Don't want to step on anyone's toes, if @sstefan1 has already started work on this, I won't pursue, unless I can somehow assist?