yousifBilal

Hi, First of, thank you for the amazing work. I have a situation where I want capture compiler directives in a SystemVerilog file. Be it an `include or `ifdef. Currently,...

Indexing arrays programatically with a variable

4

Hello, we have a case where we want to access an array element programatically: ``` (set [some_index 3]) (reval my_signal.my_array 0) ``` This however does not work. It is reading...

Hello, I am interested in using FuSoc. I would like to know if there is a way to declare my dependencies and have the tool pull it through git. Suppose...

fix event control asterisk to accept whitespace between @ and *

4

This is a fix for EventControlAsterisk to have 2 symbols @ and *. Most compilers seems to accept a whitespace between @ and *. This module was not being parsed...

This SystemVerilog code causes the parser to return an error: ```verilog property my_prop; in1 |-> ##MY_PARAM (in2 == in3); endproperty ``` Mainly because of ##MY_PARAM (in2 == in3). Removing the...