Fix sequence with parameter as cycle delay

[yousifBilal]

This SystemVerilog code causes the parser to return an error:

property my_prop;
    in1
|-> 
    ##MY_PARAM (in2 == in3);
endproperty

Mainly because of ##MY_PARAM (in2 == in3). Removing the parenthesis around in2 == in3 makes it work. The reason from what I observed is that sv-parser first tries to parse MY_PARAM into a constant function call which takes (in2 == in3) as an argument. Then causes an error because there is no sequence expression after the cycle delay.

I attempted to fix it by trying a parser for constant primary without parsing constant function, if the original parser failed.