Yanghui Ou

If my memory serves me correctly @ptpan and I imported DRAMSIM2 along with a cache from UW and tested it using pymtl3 when we were working with UW in Detroit...

hmm if we have update once would that make this easier?

Do we still want to keep the CL to RTL(val/rdy) auto-connection? If so then we may still need the fix.

Hi Kevin, There is an `is_bistruct_inst` function to check if an object is a bitstruct instance, and an `is_bitstruct_class` function to check if a type is a bitstruct class. You...

Looks reasonable to me. Another thing to try is to translate to Verilog and dump the VCD from Verilator, which supports bitstruct if I remember correctly. Best, Yanghui On Tue,...

Hi Kelvin, With PyMTL3 you don't have to switch to a "traditional" flow to use Verilator. You can translate your design to Verilog, import it back into PyMTL3, and do...

I think that is because of a limitation of the translation pass. I remember running into this issue a few years ago as well. A workaround is to change the...

Thanks for the PR. Looks good to me! Can you add a unit test in `pymtl3/datatypes/test/bits_test.py`? And perhaps a unit test for Connectables in `pymtl3/dsl/test/Slicing_test.py`?

> The test case in `Slicing_test.py` is failing, but I cannot debug the problem. To me, it looks like the `s._dsl.all_upblk_writes` cannot find variables that are in the form of...

https://github.com/pymtl/pymtl3/blob/2eb57d3c4ca87d7fdc3fda467a9a9dca294c2c75/pymtl3/dsl/AstHelper.py#L64-L65 I think you may also need to modify this (and also in the `starting_py39` function) to allow `up` and `low` to be None. Let me know if this works!