Yanghui Ou comments

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                                            Yanghui Ou

RTL gen pass fail to catch all System Verilog keyword

It is intended that we do not check for Verilog keywords when making a new `bitstruct` class, since it still works for Python simulation. We only check if the bitstruct...

Adding fst and struct trace support

Here's where we do the check: https://github.com/pymtl/pymtl3/blob/4b3bc183b14ffacd069f48dc5997b00045aea53f/pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportPass.py#L340-L347

Adding fst and struct trace support

> Is the `[0]` after a 1-bit signal in the trace added by Verilator? Or is it coming from the RTL translation pass? I think it comes from the translated...

RTL pass fail to tell value used is constant

We definitely have some degree of partial evaluation during the translation pass. For example, the free variable `t` is evaluated at the translation time and will be translated into a...

Cycle Level simulation reset function not right

Hi, Thank you for using PyMTL3. The issue is that when you call the `sim_reset()` method, the clock will be advanced, and the first few messages will be transmitted. If...

fixing verilog placeholder pass

Hmm.. As I recall we had support for this before. Not sure why it is missing?

Fix clog2 function to be fast and universal

Thank you for the PR! The change looks good to me.

23 simulation traces are not understandable for human being

The format looks great! Just a quick thought, it looks more like a "trace" than a "line trace," since "line trace" refers to a single-line trace. That said, it's perfectly...