Sean Cross

From my reading of the build outputs, doesn't `open-tool-forge/fpga-toolchain` have the exact same problem? On Windows, they rename `python.exe` to `python3-private.exe`, and they still include `lib/python3.8`. That means we could...

No, I think @edbordin is doing it correctly -- I had forgotten that I ended up shipping `python3` on Linux, which is the source of this issue. Removing `python3` and...

I built it on a Novena ages ago because it was faster than a Raspberry Pi. With recent versions of the Pi that is no longer the case, so I'm...

I created an issue in the cargo repository: https://github.com/rust-lang/cargo/issues/7984

I've already put together a simple wrapper around CSRs that I initially called `dreg`: https://github.com/xobs/dreg/blob/master/dreg.py It contains things such as `values`, which is a list of (value, description) tuples that...

> Shouldn't all CSRs be reset when the underlying core is reset as well? Having a separate reset just for registers seems odd. Yes, however it's sometimes important to have...

I've been working on `lxsocdoc` which can be inserted into a flow after verilog generation. An example of the output is available at https://rm.fomu.im/ This uses documented CSRs to generate...

How does this work for `don't care` fields? For example, in the SVD format you [can specify x](https://www.keil.com/pack/doc/CMSIS/SVD/html/elem_registers.html#elem_enumeratedValue) for values that should be marked "do not care".

I also just ran into this problem: ```python class OrderTest(Module): def __init__(self): counter = Signal(8) sig = Signal() self.sync += [ counter.eq(counter + 1), If((counter == 1) or (counter ==...

I'm also interested in uncached ibus/dbus. What would it take to port those to Wishbone?