Sean Cross

I think I see how it's supposed to work, and I've modified foboot to use the new SpiFlash-with-bitbang mode. However, the latest litex (which is required to get this mode)...

Additionally, I would like to find a path forward to enabling quad-writes. picorv32 supports bit-banging quad writes, but SpiFlash doesn't appear to support that. I'd like as-good-or-better support in an...

That's a good list of improvements! If we're asking for a wishlist of features, then an entire spi state machine would be nice. A single csr that you can write...

Yes, something like that. Maybe there's a way to connect that FSM up to the bit bang pins to get the best of both worlds? Plus, as you say, quad...

That's a very good observation! I added support for that part when I had the test jig for all of a day. It has just enough support to validate that...

The "addr" register is used to allow you to change the reset address of the CPU. For example, when debugging an .ELF file using the VexRiscv debug channel, the first...

That works, and is much nicer asthetically! The downside I see now is that with this patch, the addresses have suddenly changed and now new software is no longer compatible...

I was having a chat with @mithro, and the idea came up to use a thunked syscall interface. The idea being that you'd have a function at a well-known address,...

There needs to be a way to have `eptri` run at something other than a Wishbone frequency of 12 MHz. I'm not sure the best way to do that...

The SPI CLK signal sounds like an ECP5 quirk. If you're using the standard ECP5 SPI pins, you'll need to do a special dance to get that working: https://github.com/xobs/haddecks/blob/master/haddecks.py#L423-L425 ```python...