Joaquin de Andres
Joaquin de Andres
The value shown in the pull down resistors for the jtag writes "10k %1" and its not needed. The PN used is a resistor at 1%, future tests will allow...
The JTAG is accessible on expose IOs connector. Will be more easy if it is a separated connector. Connector 2x5 din will be added with JTAGice MkII layout: 
General check of silk screen. Version update on silk screen.
When we change the design from eagle to kicad some holes disappear.
The BOM is not fully defined. We will copy the components that are defined in the eagle design and define thous that are not.
In the future we want to use the magnetics in a separated board for quick exchange. Further discussion needs to be made on this matter.
There are some power domain that can be isolated for enhance general power domain noice. The next power domains will be separated with choke inductor: * PCIe0 and PCIe1 3.3V...
There are some vias and tracks not in the best shape. Vias will be ordered. Extra tacks will be deleted. Power tracks will be changed to zones. Further discussion is...