Joaquin de Andres

There is a jtag header for mips microprocessors https://www.linux-mips.org/wiki/JTAG Will change the connector pinout to be compliant with this. 1 nTRST (not present, a pad will be left for future...

Change C6, C57-C59, C75, C110, C111, C116, C124 from "0.1uF" to "0.1uF, 10V". So we can use same component as C5, C10-C13, C21, C30, C33-C35, C37, C42, C62, C71, C72,...

For C40, C41, C49 (10nF, 2KV) I only found https://eu.mouser.com/ProductDetail/Yageo/CC1812JKX7RDBB103?qs=tS%2FAHvPQ%2F55AosBJ0y7d0A%3D%3D

Changed to: https://www.digikey.com/product-detail/en/murata-electronics/GCJ31CR73A103KXJ3L/490-16694-6-ND/7595929

For C18, C27, C43, that are defined as Nichicon_6.6x7.7 a taller replacement will be used: https://www.digikey.com/product-detail/en/nichicon/UCM1A471MCL1GS/493-14524-6-ND/5800270

Inductors L2-L5, L8 part number lead me to https://www.datasheets360.com/part/detail/swpa6045s6r8mt/-8277091879156552518/  With thous characteristics I found: https://www.digikey.com/product-detail/en/abracon-llc/ASPI-6045S-6R8M-T/535-13046-6-ND/5413867 This is ok?

Like a self reset? or like suicide?

Ok, so the GPIO is an external GPIO.  We can add there a PMOS transistor like:  with the same transistors that we are using for POE.

Taking advantage of the power domains division a general review of capacitance will be performed.

There is not an specific problem with this. Maybe getting this done introduces more problems.