Wilson Snyder

As to comment in #6627: The first LinkDot will set the :: references to modules that are not parameterized, and provide other hints for V3Param to work. Then V3Param runs...

The first LinkDot in other cases sets the appropriate classOrPackageNodep to pass to later stages, so presumably similar would work here. (Or, it was intended to do so already, and...

Also note V3Combine and V3Reloop exist only to try to make the code more compact, but both are very simplistic compared to what they could do. We could also add...

My quick read is it's treating G_DMI_ADDRESSES_MASK as if it's a packed array, which it is not. Almost certainly the warning and error are symptoms of the same problem (whatever...

BTW to help making sure these get fixed appropriate can you please edit the example to an initial block that makes the test self checking, e.g. tests values of dmi_addr_match?...

I added an assert so it at least doesn't segfault, @igorosky I'm presuming you'll make a pull to resolve? Thanks in advance.

The 'static' issue is probably same or related to #6750

verilog.y has this: https://github.com/verilator/verilator/blob/c5f8656aa02db37776967f34806d8bc1718a7eb9/src/verilog.y#L4917-L4923 This parser hack will need to be fixed to resolve the conflict, and the test added.

Note a normal `foreach` is supported, try rewriting it as an equation without the implication by moving the foreach upward. e.g. foreach(haddr[i]) hsize == AHB_SIZE_16 && haddr[i][0] == 0;

Moving to a data table will require calculating intermediate values always, which I prefer not do. Referring to this code example ``` module sub (input in); endmodule module t; reg...