Wilson Snyder
Wilson Snyder
After V3LinkCells, remove all AstConfig.
Currently V3LinkCells makes a graph with vertexes as the module names, and edges representing dependencies. Edges are of many times and indistinguishable, but you could use a custom weight for...
Seems like a great plan, I look forward to the pull - that will be easier to review, at present I see only minor style comments. > Implement the V3LibMap...
Blocked by #2412, which fix is being worked on, then needs additional fix.
No longer blocked by #2412. Issue is now that typedef which is of a parameterized class gets resolved before the class is parameterized. This is a workaround: ``` - automatic...
Will you contribute a pull? More seriously, yes, eventually, but we have many issues, but not enough time ;)
Another smaller example: ``` package uvm_pkg; class uvm_reg_sequence #( type BASE = int ); typedef enum { LOCAL, UPSTREAM } seq_parent_e; endclass endpackage module t; import uvm_pkg::*; class test_seq extends...
This appears to be because the wrapTopCell is skipped with json-only-output (intentionally so the output doesn't have the fake internal wrapper), and as such the port doesn't get marked with...
>Not sure how to make "include" unsupported in verilog files, but supported in libmap. I guess it would have to be a modified lexing rule? Correct.
Once tests are passing, please add github pr:dev-coverage label, then when resuls pop out, check the report for any lines/branches that need additional testing to cover. Thanks.