Wilson Snyder

No, if something needs to be contributed to Verilator it must be done in this repo.

Looked at implementing 2D and made a test below. At least two commercial simulators don't support this, so implementing it will remain a low priority, but as always pull requests...

Might be straightforward, V3Inst unrolls 1D arrays and renames to `__BRA__#__KET__`, so hopefully improving that file is sufficient. There's the test above for normal instances, also use --trace and check...

Testcase in our format: ``` `timescale 1ns / 1ps module t; reg [7:0] dlycyc; reg [7:0] cyc = 1; logic test_clk = 0; initial begin $display(" t (ns) dlycyc"); $display("--------------");...

The problem appears to be that the delayed assignment is using the future value of cyc instead of the old value. Changing it to this I get correct results: ```...

There's no current clean way to do this. One perhaps easy but ugly hack is to write a pipe-filter that when parsing "driver" replaces "sub" with "sub_1", and when parsing...

Attached is the patch to get started. This applies on the current master 8965401d10e3b78b8b0b823a35304cf690b01b7e [config.patch.txt](https://github.com/user-attachments/files/19495769/config.patch.txt) I wouldn't call this even 10% What would first be appreciated is a pull that...

Great, I added some t_config tests to master, they just error out currently. There's several ideas in there, some notes: 1. Make `--work` properly pick modules. 2. Change `--top` to...

Yes, I think you need to handle all config first. I think they all get added directly under the netlist so the new stage can be just a for loop...

It's not using config at all, it simply assumes whatever library this module was in (based on --work setting the libname()) is where to look now.