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The marked up schematic page 1, to reflect the assembly: 

It depends on the loading. Do you have any data from the Xilinx Power Estimator for how much current is drawn on the +1.0V, +1.2V, +1.5V, and +1.8V rails?

Looking at "Timingcard_SCHEMATICS_BETA_V1.pdf", the AT24MAC402 serial EEPROM WP input (p. 4,A5) is driven by the EXT_EEPROM_WP signal from the FPGA board (pin P1A-44, p. 6,B5) and a 10K pullup to...

EEPROM write protect is +1.5V signal in new FPGA description File: PinoutConstraint.xdc, lInes: 75-77 ``` #EEPROM set_property PACKAGE_PIN V9 [get_ports EepromWp_DatOut] set_property IOSTANDARD **LVCMOS15** [get_ports EepromWp_DatOut] ```

Fixed in subsequent versions.

Issues addressed in subsequent documents.

**Not fixed** in file: Time-Appliance-Project/blob/master/Time-Card/FPGA/Open-Source/Implementation/Xilinx/**TimeCard**/Constraints/PinoutConstraint.xdc **Is fixed** (moved to pin AA13) in file: Time-Appliance-Project/blob/master/Time-Card/FPGA/Open-Source/Implementation/Xilinx/**TimeCard_Production**/Constraints/PinoutConstraint.xdc

Fixed in recent FPGA pushes.

Addressed in bracket V4 docs.

Still not fixed in "Prototype V7" schematics Ref: file "Timingcard_PROJECT.pdf", in Time-Card/HW/ECAD/Prototype-V7/ECADv7.7z"