Catherine
Catherine
Denominating from 0.3 milestone since implementing this well requires a fairly significant rewrite of the internals. Perhaps that would be a good thing to do in 0.4.
`write_verilog -sv` is included in the 0.10 release, required as of today, so this can be implemented now.
I would strongly prefer it if there was only a single `invert` property, containing a tuple of booleans or perhaps more nicely a single `int` that can be XOR'd in...
> In the DSL? Internally. Let me review your changes more carefully first, though.
On Linux, Glasgow uses hotplug detection since it's available in libusb, so #239 shouldn't apply...
The [Cyclone-V handbook](https://www.mouser.com/pdfDocs/cv_5v2.pdf) says: > If you use the internal oscillator, you can choose a 12.5, 25, 50, or 100 MHz clock under the Device and Pin Options dialog box,...
For context, I tried implementing this and it didn't work out well due to the way "fragment transformers" are currently used. We should get rid of those and then implement...
Sadly, yes. Most of the AST transformation stuff should be ripped out and replaced with a fairly typical lexical scope mechanism. That would make elaboration several times faster, make local...
Okay, @bracketmaster relays it from the folks at Chip11 that this issue was the biggest pain point for them while learning. I think that's a solid indication that I should...
I think it would be very useful to have cheap adapters to/from both AXI4-Stream and Avalon-ST, so it makes sense to restrict the features provided by nMigen streams to a...