Catherine
Catherine
> I think I'm slightly less enthused about non-octet data streams than you are In my view, non-octet data streams are not particularly *inherently* valuable, but their value comes from...
> With a good library of base elements: Converter/FIFOs/Mux/Demux/Gearbox/etc... + #213 on top, it could becomes very powerful! LiteX has certainly been an inspiration for this. I suspect the final...
I agree that functionality similar to what you propose can be useful. However, at the moment I find it more important to have feature parity between pysim and cxxsim, and...
@programmerjake Would it help if you were able to print debug messages, similar to Verilog's `$display`, from both HDL and your testbenches? Because *that* functionality fits much better into the...
I think we could hack something so that `$display`'d messages go into VCD files or otherwise end up in gtkwave-parseable form. It's going to be quite gross but by this...
> then tell the c++ vcd writer to write an event to a specified var So, currently you can't do that. The C++ VCD writer is sampling the state of...
Here's my proposal: once `Display`/`$display` are added to nMigen/Yosys and implemented in pysim/cxxsim, let's take another look at this feature, and hopefully implement it using the same mechanisms. Sounds good?
Reopening since `Display` will likely force the necessary refactoring to be done early.
Expected issue. Fix is not planned until the entire middle-end is converted to use a netlist-style representation but the bug will be kept open in the meantime.