Catherine
Catherine
CXXSim no longer ignores contract violations, and uses an appropriate method to reset the simulation. Prepending the `top` module in CXXSim VCD files will require upstream changes, see new task...
VCD hierarchy in CXXSim and PySim now matches.
CXXSim now writes GTKW files.
CXXSim will not support race-free memory read/write operations; see https://github.com/nmigen/nmigen/issues/531#issuecomment-740512280 for details.
In general, if the simulator doesn't converge, it means an issue with the input netlist. I'd say that the appropriate way to handle this is to reject such netlists before...
That's completely unintentional--the FSM states are supposed to be strings only at the moment. I agree that having enum variants be usable as FSM states would be a nice feature.
> * Minimal hassle to invoke `symbiyosys` that "does the right thing" on a `Fragment` or `Module` (`Elaboratable`). It's not clear that there is a single "right way" to invoke...
> I'd like to see this coupled with simulation Platforms as well. It's not entirely clear what a formal/simulation platform would *do*. Currently, the main job of a platform is...
> Before any of the changes discussed here, this basically means giving you whatever I/O you request, no questions asked, in a usefully simulable way, to the greatest extent possible....
> if a platform has assertions, then that platform can't be used for synthesis Oh. But it would actually be really nice if assertions could be used for synthesis, because...