Integrate the CXXSim simulator

[whitequark]

A while ago I've implemented the Yosys cxxrtl backend, which is very similar to the current Python simulator conceptually while being significantly (10-100×) faster, competitive with Verilator.

nMigen should tightly integrate with this simulator, providing an interface identical to that of nmigen.sim.pysim.

CXXSim is currently developed in the cxxsim branch. You are encouraged to try it and report results!

Remaining tasks

See also https://github.com/nmigen/nmigen/issues/531 for Yosys-side view of these tasks.

Blockers (to be completed pre-merge)

• [x] CXXSim currently builds with -DNDEBUG because RTL contract violations (e.g. out of bounds memory reads) must not crash the host Python process. CXXRTL's VCD library currently ignores contract violations in NDEBUG builds, potentially hiding bugs.
• [x] CXXRTL design is reset (in response to a simulator reset) in an unreliable way because of missing CXXRTL-side API
• [x] VCD hierarchy does not match PySim's (missing top module)
• [x] .gtkw files are not written
• [x] write_vcd(traces=) are ignored
• [x] Reset values of undriven values are ignored
• [x] Simulator-only signals are not present in VCD files (#556)
• [x] Resetting CXXRTL design corrupts debug information (#565)
• [ ] CXXRTL-side Memory reads/writes from Python testbenches are not implemented in CXXSim (#564)
• [ ] Python testbenches trying to wait on CXXRTL values of certain types trigger assertion failures

Non-blockers (may be completed post-merge)

• [ ] Driving CXXRTL-side clocks of type WIRE does not trigger edge-sensitive logic connected to the clock; only driving clocks of type VALUE works properly
• [ ] Enumerated signals appear in their raw form in CXXRTL-generated VCD files
• [ ] Compilation fails out of box on macOS (https://github.com/nmigen/nmigen/issues/495); probably on other platforms too
• [ ] Display (https://github.com/nmigen/nmigen/issues/432)
• [ ] Assert (https://github.com/nmigen/nmigen/issues/427)

[cestrauss]

As the cxxsim work nears completion, I would like to point out some remaining issues, so they are not missed:

• In the VCD file generated by cxxsim, there is no top module, like in pysim. This means the same GTKWave document can't be used for both.

• Enum traces are not supported (the numerical values are recorded instead).

• There are still a couple of FIXMEs in write_vcd (write the gtkw_file and use the traces parameter).

[whitequark]

CXXSim no longer ignores contract violations, and uses an appropriate method to reset the simulation.

Prepending the top module in CXXSim VCD files will require upstream changes, see new task in #531.

[whitequark]

VCD hierarchy in CXXSim and PySim now matches.

[whitequark]

CXXSim now writes GTKW files.

[whitequark]

CXXSim will not support race-free memory read/write operations; see https://github.com/nmigen/nmigen/issues/531#issuecomment-740512280 for details.

[robtaylor]

I'm happy to have a look at it on mac when time is right..