Catherine
Catherine
I'm not sure how specifying the location would help? Having two clocks with a phase offset however should be easily expressible via the same approach of using equations, just for...
I think this is a reasonable plan.
> Should the interface require you to specify the tolerance for error? Yes, since the constraint solver would have to take this into account anyway.
> The shape of the solver is based on algorithms found in migen's [clock.py](https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/clock.py). That's not migen, that's litex.
> re aliasing: The ripple counter's length is essentially unlimited, right? (Limited only by FPGA size.) So you can make something obscenely large, like a 32 bit counter, and run...
> if the `remote-build` feature is enabled You can't detect that, as far as I know.
> I think it is good to consider how this interfaces with code documentation with tools like Sphinx? Sphinx will pick up the annotation and the docstring for it if...
> I think that a rich-enum layout would be really great as well—something like a union with the tag built in. I agree entirely! I think that discriminated unions (rich-enums,...
> `op.tag` or `op.kind` makes sense to add in my opinion. That would work. Your code would define an enum `Op.Tag` with values `Op.Tag.MUL_ADD` and so forth, along with an...
> How would per-field reset values be defined for aggregate signals ? (also: `reset_less`, `attrs`) `reset_less` and `attrs` are not possible to implement per-field since there is not a distinct...