Vanessa McHale

Hi, Now that `bytestring` is at [0.11.0.0](http://hackage.haskell.org/package/bytestring), the bound could be loosened to include it. This works on my computer and would help in my [webp](https://hub.darcs.net/vmchale/webp) project. Thanks :)

This allows building via GHC 8.6.3, among other things.

Tighter bounds base for old cmdargs

1

Visible on Hackage [Matrix CI](https://matrix.hackage.haskell.org/#/package/cmdargs). This breaks builds for compilers that don't support TemplateHaskell (e.g cross-compilers for GHC 8.6.5)

Add Xilinx dual clock FIFO primitive to `clash-cores`

20

This adds Xilinx's DcFifo to clash-cores. The Haskell model and the IP are both tested. Past discussion is [here](https://github.com/clash-lang/clash-compiler/pull/2182#issue-1222094757); it is bit cluttered. It's a draft PR because it depends...

Vivado test infrastructure fails on Parameters

7

``` ERROR: [XSIM 43-3225] Cannot find design unit topEntity.testBench in library work located at xsim.dir/work. ``` It seems to try to simulate `topEntity.testBench` instead of `testBench.testBench`, see https://github.com/clash-lang/clash-compiler/pull/2257#issuecomment-1172957230

Memory files in Vivado

1

Vivado test fail on `RomFile`: https://github.com/clash-lang/clash-compiler/pull/2257#issuecomment-1173154137 We can do something more sophisticated in our Vivado tests to get this working: https://github.com/clash-lang/clash-compiler/pull/2257#issuecomment-1173159368

Vivado test trips up on AndSpecificEnable

1

It gives the following result: ``` Error: outputVerifier, expected: 000000010000000100000001, actual: 000000010000000000000000 Time: 40 ns Iteration: 1 Process: /testBench/r_assert/line__245 File: /tmp/clash-test-a14a5f544b110810/AndSpecificEnable.testBench/testBench.vhdl Error: outputVerifier, expected: 000000110000001000000010, actual: 000000110000000100000001 Time: 60 ns...

Vivado test trips up on BlobVec

1

It gives different results in simulation: ``` Error: outputVerifier, expected: 000000000000000100010000, actual: 000000000001000000100000 Time: 10 ns Iteration: 1 Process: /testBench/r_assert/line__194 File: /tmp/clash-test-e6fd091d2363ea54/BlobVec.testBench/testBench.vhdl Error: outputVerifier, expected: 000000000000000100010000, actual: 000000000001000000100000 Time: 20...

We can't simulate in Vivado: ``` ERROR: [XSIM 43-4287] "/tmp/clash-test-5711c4217d9c0815/I2Ctest.I2CConfig.config/configi2c.v" Line 400. Undefined system task '$finish_and_return' ```

Right now, the test suite takes e.g. `PortProductsSum_testBench` as an argument to `BuildSpecific`. That makes it needlessly complicated to find the `clash-manifest.json` for a particular entity (here, `verilog/PortProductsSum.topEntity/clash-manifest.json`). We should...