veryl

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20

Consider ```systemverilog module test ( input [2:0] onehot, output logic [1:0] idx ); always_comb begin case (onehot) 3'b001: idx = 2'b01; 3'b010: idx = 2'b10; 3'b100: idx = 2'b11; endcase...

nblei

[Feature] Function with args of which type is interface

1

考えがちゃんとまとまっていないので、日本語で。 virtual function であれば関数の引数にすることとができるが、それでは RTL 中で使えない。 * 合成できるか不明 * `always_comb` とかで使う際に、イベントを推定できない(と思う) Veryl 上で、interface を引数に取る関数を定義した場合、SV に出力する際に interface 中の各信号を引数に取る関数定義に書き換えてやればよい。 例えば、以下のようなコードの場合、 ```systemverilog interface foo_if #( param WIDTH: u32 = 8. ){ var ready:...

taichi-ishitani

`unused_variable` error for a variable referred as LHS only

1

Currently, Veryl does not report `unused_variable` error for a variable referred as LHS only like below.  Should Veryl report the error for this?

taichi-ishitani

Combinational loop should be resolved but Veryl does not check it. 

taichi-ishitani

Should Veryl add `automatic` lifetime modifier to variables declared in statement block within `always_ff`/always_comb` statement? refs: https://github.com/veryl-lang/veryl/issues/919#issuecomment-2323581787

taichi-ishitani

If interface can have interface instances as the member, interface composition can be achived like below. Syntax and use case should be more considerd. ```systemverilog interface Read { } interface...

dalance