veryl
veryl copied to clipboard
veryl-lang
Veryl: A Modern Hardware Description Language
Dalance, Not sure if there's interest, but a nice feature may be emitting SystemVerilog with back annotations of some sort. While this would help humans who are performing verification to...
Dalance, I would like to add a type checking pass which has a primary goal of evaluating the size (in bits) and packedness of each datatype. The way I see...
Modern standard cell libraries include flops with asynchronous sets. For example, DC maps ``` module f( input clk_i, input rst_ni, input set_i, input q_i, output reg q_o ); always_ff @(posedge...
Hey Dalance, what do you think of the idea of doing a tutorial or workshop at ASPLOS (https://www.asplos-conference.org/asplos2024/cfp/) or similar architecture / EDA conference? Personally I think Veryl has the...
Motivations: There always be some targets other than *.sv files need to be generated in the project. For example, some SDC files. And they should go with project and could...
This is a language feature proposal. Incorporating the ability to publish projects and add dependencies similar in spirit to Rust is a great addition to Veryl. However, one current limitation,...
I'd like to introduce begin/end less range expression. This is an example: ``` var a: logic; var b: logic; b = inside a {..8}; // a inside {[$:7}]; b =...
