Veripool API Bot

--- Original Redmine Comment Author Name: **Greg Hilton** Original Date: 2015-08-11T21:44:55Z --- Some how my request got submitted before I finished filling it in; and I cannot edit :( Basically...

--- Original Redmine Comment Author Name: **Alex Reed** Original Date: 2015-08-12T12:39:52Z --- I like this idea (and I've even thought about implementing it before...) As you mention, this is only...

--- Original Redmine Comment Author Name: **Alex Reed** Original Date: 2016-02-19T19:32:00Z --- From Kaushal Modi in www.veripool.org/issues/1038-Verilog-mode-Support-for-named-ends-Example-endclass-CLASSNAME- ``` Hi, I was leaning towards getting auto named ends functionality just like...

--- Original Redmine Comment Author Name: **Kaushal Modi** Original Date: 2016-02-19T20:36:07Z --- Cool! Any idea about that **unless** condition?

--- Original Redmine Comment Author Name: **Kaushal Modi** Original Date: 2016-02-21T04:53:17Z --- I missed reading these lines earlier when I posted that reply: > Further review shows that the (unless...

--- Original Redmine Comment Author Name: **Wilson Snyder** (@wsnyder) Original Date: 2017-11-19T13:26:53Z --- Still missing feature AFAIK, perhaps someone would like to contribute a patch?

--- Original Redmine Comment Author Name: **Wilson Snyder** (@wsnyder) Original Date: 2010-12-16T18:40:38Z --- Thanks for filing.

--- Original Redmine Comment Author Name: **Michael McNamara** Original Date: 2011-02-21T02:21:40Z --- Hmm, this is way difficult. I like Wilson's idea of using verilog-typedef-regexp as the single way to tell...

--- Original Redmine Comment Author Name: **Wilson Snyder** (@wsnyder) Original Date: 2012-03-06T02:22:27Z --- The regexp was removed about a year ago. I believe it was rev679. Please confirm if you...

--- Original Redmine Comment Author Name: **Wilson Snyder** (@wsnyder) Original Date: 2012-03-07T00:22:52Z --- Mac, any thoughts on this?