Veripool API Bot

--- Original Redmine Comment Author Name: **Ian Perryman** Original Date: 2016-06-27T14:18:36Z --- Does this feature work for anyone? I could not get it to work in emacs 23.1 or 24.1...

--- Original Redmine Comment Author Name: **Wilson Snyder** (@wsnyder) Original Date: 2016-07-09T18:21:58Z --- Looking at the git history, this code was designed for Emacs 19. Given the error this must...

--- Original Redmine Comment Author Name: **Ian Perryman** Original Date: 2016-07-11T14:43:21Z --- Hi Wilson, I will see what I can do. First I have to figure out what the right...

--- Original Redmine Comment Author Name: **Wilson Snyder** (@wsnyder) Original Date: 2016-07-14T02:48:41Z --- We generally try to keep as many versions as possible, but I think think in this case...

--- Original Redmine Comment Author Name: **Wilson Snyder** (@wsnyder) Original Date: 2017-11-19T14:00:11Z --- AFAIK this is still an issue.

--- Original Redmine Comment Author Name: **Wilson Snyder** (@wsnyder) Original Date: 2018-05-30T10:38:16Z --- There is some code in place to skip over the clocking. Can you attach a self-contained test?...

--- Original Redmine Comment Author Name: **David Rogoff** Original Date: 2018-05-30T18:14:36Z --- Before expansion: ``` module clk_rst_gen (output logic clk, rst); default clocking tb_cb @(posedge clk); default input #1step output...

--- Original Redmine Comment Author Name: **Wilson Snyder** (@wsnyder) Original Date: 2018-06-01T12:24:46Z --- I made a stab at this but it needs more time as broke clocking modports. Basically the...

--- Original Redmine Comment Author Name: **David Rogoff** Original Date: 2019-07-15T19:07:46Z --- Hi Wilson. I just hit this problem again and wondered if there's been any activity on it during...

--- Original Redmine Comment Author Name: **Wilson Snyder** (@wsnyder) Original Date: 2016-08-30T01:02:56Z --- Rather than a force, which is sort of a don't not include something, how about a verilog-auto-subdecl-regexp...