verilog-mode

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emacs expansion of a large auto-templated file fails with no hints on where the error - DEBUG METHODS

1

Hi verilog-mode team Problem: I have a large RTL with extensive AUTO_TEMPLATE being used. Sometime when there are multiple AUTO_TEMPLATED edited the emacs verilog-mode expansion fails with the error as...

engrvns

Hi verilog-mode team Is there a way to have verilog-mode AUTO_TEMPLATE print the originating port/module of a signal connected to an input port. Notice the comments right next to the...

engrvns

alignment and indentation issue with import and "=" for localparam

3

--- Author Name: **Enzo Chi** Original Redmine Issue: 1272 from https://www.veripool.org --- I am using verilog-mode from commit "c579c46" and set "verilog-auto-lineup" to "all" Example code: ``` module alignment_test import...

veripoolbot

Is there a variable to control in which column a port name appears?

4

I searched through the customizable variables listed on https://veripool.org/verilog-mode/help/ but did not find one that would control the column in which a port name declaration appears. It would be desirable...

cswfb

'verilog-mark-defun' does not mark functions

2

Hi, According to the docstring of `verilog-mode` and `verilog-mark-defun` this function should mark functions. However, since function/task regexps do not belong to `verilog-defun-re` and `verilog-end-defun-re`, `verilog-mark-defun` marks whole modules, classes,...

gmlarumbe

SystemVerilog interface indentation in module declaration

2

--- Author Name: **Clarke Watson** Original Redmine Issue: 1446 from https://www.veripool.org --- Hi, Thanks for creating and maintaining verilog-mode. It is awesome! I am having trouble getting SystemVerilog interfaces inside...

veripoolbot

Fontifying of variable names in declarations not working correctly

6

I'm not sure how no one has brought this up yet, but it seems that something is definitely wrong with the code to recognize and fontify variable names in declarations....

fnJeff

verilog-mode-map rebinds delete and backspace keys

3

I don't think the mode should do that since many people (me included) already have custom keybindings defined for those keys. Afaict, most other major modes leave those keys alone.

bjourne

fix: should able to declare the input as wire

4

We appreciate your contributing to Verilog-Mode. By contributing you agree this code will be licensed under the GNU Public License. Please check your github name is set to your real...

kopinions

AUTOINPUT can not create signal with nettype

1

Code snippet like below `/*AUTOINPUT*/` generated like below ``` input a; input [7:0] b; ``` the setting is below ``` verilog-auto-declare-nettype="wire" verilog-auto-wire-type="wire" ``` after some investgation, it seems that when...

kopinions