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20 hours ago •
ultraembedded
ultraembedded
Various HDL (Verilog) IP Cores
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For me uart_cfg_div does not get set:  Moreover above vardump diverges from what $display outputs: ``` rst_i = 0, write_en_w = 0, addr_i = 0, data_i = 15 rst_i...
…bled Previous behaviour before this fix has two consequences: 1. First cell in memory is filled without cfg_enabled. 2. Since after that write_detect_q is on then it causes buffer_full_q on...